Guilherme Korol

Hi! My name is Guilherme dos Santos Korol, I work as an AI/ML compiler engineer at the AI Competence Center at NXP Semiconductors. My research/work topics are Compilers and Computer Architecture for Deep Learning.

More about me:

From May 2024 to July 2025 I worked as a postdoctoral researcher at the Chair for Compiler Construction (CCC) at the Computer Science Department of TU Dresden. My postdoc activites were centered around the Myrtus EU Project, particularly within the Design and Programming Environment pillar. During that time, I have also worked on a compiler-supported optimization technique for skipping layers/blocks of Deep Neural Networks (DNN).
Before all that, I carried out my PhD with the Computer Science program at the Federal University of Rio Grande do Sul (UFRGS) in Brazil. There, I worked under the supervision of Professor Antonio Beck. Between September 2022 and April 2023, I was also with the CCC under the supervision of Professor Jeronimo Castrillon. In that time, my work targeted efficient execution of DNNs on FPGAs. I investigated how optimization methods (from the ones at the hardware level like approximate computing and HLS to the ones at the DNN level like pruning, quantization, and early-exit) can improve the FPGA execution of DNNs - especially under constrained environments like the IoT-edge.

For my MSc degree (from 2019 to 2020), I joined the Microelectronics program at UFRGS working on general-purpose reconfigurable computing. I received my BSc. in Computer Engineering from the Pontifical Catholic University of Rio Grande do Sul (PUCRS) in 2018. Part of my bachelor (three terms) was taken at the University of Colorado at Denver (CU Denver). Back then, as a bachelor student, I took part in my first research project as a research intern at the Capitol Technology University (Laurel/MD) at the end of my exchange at CU Denver. This project was a partnership with NASA’s Goddard Space Flight Center. After the exchange, I worked on a few other research projects, like designing a full-VHDL CNN accelerator for my final bachelor project

See more details and a full list of my projects here and their resulting publications here.